The present invention relates generally to semiconductor devices and the fabrication thereof and, more particularly, to an asymmetric semiconductor device having a dual work function gate.
A pervasive trend in modern integrated circuit manufacture is to produce semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), that are as small as possible. In a typical MOSFET, a source and a drain are formed in an active region of a semiconductor layer by implanting N-type or P-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer. It is noted that MOSFETs can be formed in bulk format (for example, the active region being formed in a silicon substrate) or in a semiconductor-on-insulator (SOI) format (for example, in a silicon film that is disposed on an insulating layer that is, in turn, disposed on a silicon substrate).
Although the fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate for the formation of relatively large circuit systems in a relatively small die area, this downscaling can result in a number of performance degrading effects. In FET devices with a channel having a relatively short length, the FET can experience a number of undesirable electrical characteristics referred to as short channel effects (SCE). SCE generally occur when the gate does not have adequate control over the channel region, and can include threshold voltage (Vt) roll-off, off current (loff) roll-up and drain induced barrier lowering (DIBL). As the physical dimensions decrease, SCE can become more severe. SCE is the result of intrinsic properties of the crystalline materials used in the FET devices. Namely, the band gap and built-in potential at the source/body and drain/body junctions are non-scalable with the reduction of physical device dimensions, such as a reduction in channel length.
A typical technique used to minimize SCE is to fabricate FETs with extensions as part of the source/drain areas. The extensions are commonly formed using a lightly doped drain (LDD) technique as is well known in the art.
In addition, achieving a desired device dimension is often difficult as device designers are constrained by limitations imposed by various manufacturing techniques. For example, photolithography is often used to pattern a mask layer that is used to determine the size and placement of device components, such as the gate. However, lithographic limits restrict gate formation to a certain minimum length.
Accordingly, there exists a need in the art for semiconductor devices, such as MOSFETs, that have a reduced scale and reduced SCE. In addition, a need exists for fabrication techniques for making those semiconductor devices.
According to one aspect of the invention, an asymmetric semiconductor device including a source and a drain formed in a layer of semiconductor material and a gate disposed on the layer of semiconductor material to define a channel interposed between the source and the drain, the gate including a gate dielectric and a gate electrode, the gate electrode spaced from the layer of semiconductor material by the gate dielectric. The gate electrode includes a first gate electrode portion having a first work function and for controlling a region of the channel adjacent the source and a second gate electrode portion adjacent the first gate electrode portion and having a second work function different from the first work function and for controlling a region of the channel adjacent the drain.
According to another aspect of the invention, an integrated circuit including an asymmetric NMOS device and an asymmetric PMOS device. The asymmetric NMOS device has a first source and a first drain formed in a layer of semiconductor material and a first gate disposed on the layer of semiconductor material to define a first channel interposed between the first source and the first drain, the first gate including a first gate dielectric and a first gate electrode, the first gate electrode spaced from the layer of semiconductor material by the first gate dielectric. The first gate electrode includes a first source side electrode portion made from a mid-gap material and having a first work function and a first drain side gate electrode portion adjacent the first source side gate electrode portion and made from an N+ doped semiconductor material to have a second work function different from the first work function. The asymmetric PMOS device has a second source and a second drain formed in the layer of semiconductor material and a second gate disposed on the layer of semiconductor material to define a second channel interposed between the second source and the second drain, the second gate including a second gate dielectric and a second gate electrode, the second gate electrode spaced from the layer of semiconductor material by the second gate dielectric. The second gate electrode includes a second source side electrode portion made from the mid-gap material and having the first work function and a second drain side gate electrode portion adjacent the second source side gate electrode portion and made from a P+ doped semiconductor material having the same base material as the N+ doped semiconductor material and having a third work function different from the first work function.
According to yet another aspect of the invention, the invention is a method of fabricating a pair of asymmetric semiconductor devices each having a dual work function gate. The method includes providing a layer of semiconductor material; forming a layer of gate dielectric material on the layer of semiconductor material; forming a dummy gate having a pair of sidewalls on the layer of gate dielectric material; forming a first gate electrode portion adjacent each sidewall of the dummy gate; removing the dummy gate; and forming a second gate electrode portion adjacent each of the first gate electrode portions such that respective pairs of first and second gate electrode portions form a gate electrode for each of the asymmetric semiconductor devices.